/////////////////////////////////////////////////////////////////////////////////
// Company: Arizona State University
// Engineer: Kyle D. Gilsdorf
//
// Create Date: 08:07:29 11/04/2011
// Design Name: 
// Module Name: seg_display
// Project Name: Lab #2
// Target Devices: 
// Tool versions: 
// Description: The 7-Segment LED Display module drives the 4 separate LED
// 7-Segment LED Display devices mounted on the FPGA Board.
//
// Dependencies:
// - my_clock
//
// Revision 0.01 - File Created
// Additional Comments:
// - I have provided the entire alphabet so that you can change this to display
//   other text as well.
/////////////////////////////////////////////////////////////////////////////////
module slowclock 
  /*************************************************************************
   * Input/Output Declarations and Parameters                              *
   *************************************************************************/
  (// Global Signals                  // -----------------------------------
   input  wire clk,                   // System Clock
   output wire clk_800Hz);            // 

   parameter MSB = 16;

  /***********************************************************
   * Signal Declaration                                      *
   ***********************************************************/   
   reg [MSB:0] count1 = 0;

  /***********************************************************
   * Combinational Logic                                     *
   ***********************************************************/
   assign clk_800Hz = count1[MSB];

  /***********************************************************
   * Synchronous Logic                                       *
   ***********************************************************/
   always@(posedge clk)
      count1 <= count1 + 1'b1;
	  
  /***********************************************************
   * Module Instantiation                                    *
   ***********************************************************/	  
endmodule

module sev_seg_disp(
	 input rst, clk_50mhz,
    input [3:0] read_data,
	 output reg read = 1'b0,
	 output wire [1:0] addr,
	 output reg [6:0] led_dis = 7'b1111111,
	 output reg [3:0] dis_control = 4'b1111
  );
	 
	 reg [6:0] disp_data_0 = empty;
	 
   ///////////////////////////
   // 7-Segment LED Display //
   //       aaaaaaaa        //
   //      f         b      //
   //      f         b      //
   //      f         b      //
   //      f         b      //
   //       ggggggggg       //
   //      e         c      //
   //      e         c      //
   //      e         c      //
   //      e         c      //
   //       ddddddddd       //
   ///////////////////////////
   //                   6543210
   //                   gfedcba
   parameter _0_   = 7'b1000000;
   parameter _1_   = 7'b1111001;
   parameter _2_   = 7'b0100100;
   parameter _3_   = 7'b0110000;
   parameter _4_   = 7'b0011001;
   parameter _5_   = 7'b0010010;
   parameter _6_   = 7'b0000011;
   parameter _7_   = 7'b1111000;
   parameter _8_   = 7'b0000000;
   parameter _9_   = 7'b0010000;
   parameter A     = 7'b0001000;
   parameter B     = 7'b0000011;
   parameter C     = 7'b1000110;
   parameter D     = 7'b0100001;
   parameter E     = 7'b0000110;
   parameter F     = 7'b0001110;
   parameter empty = 7'b1111111;
	
	//wire clock_10Hz;
	reg [1:0] count = 1'b00;
	
	assign addr = count;

	always @(posedge clk_50mhz, negedge rst) begin

		if (~rst) 
			begin
				disp_data_0 <= empty;
				read <= 1'b0;
			end

		else 
			if (clk_50mhz)
				begin
					read <= 1'b1;
					case (read_data)
						4'h0 : disp_data_0 <= _0_;
						4'h1 : disp_data_0 <= _1_;
						4'h2 : disp_data_0 <= _2_;
						4'h3 : disp_data_0 <= _3_;
						4'h4 : disp_data_0 <= _4_;
						4'h5 : disp_data_0 <= _5_;
						4'h6 : disp_data_0 <= _6_;
						4'h7 : disp_data_0 <= _7_;
						4'h8 : disp_data_0 <= _8_;
						4'h9 : disp_data_0 <= _9_;
						4'hA : disp_data_0 <= A;
						4'hB : disp_data_0 <= B;
						4'hC : disp_data_0 <= C;
						4'hD : disp_data_0 <= D;
						4'hE : disp_data_0 <= E;
						4'hF : disp_data_0 <= F;
						default : disp_data_0 <= empty;
					endcase
				end
			else 
				read <= 1'b0;

	end

	always @(posedge clk_800Hz or negedge rst) begin
      if (~rst) begin
			count <= 2'b00;
         led_dis <= empty;
         dis_control <= 4'b1111;
      end
      else begin
         count  <= count + 1'b1;
         case (count)
            0 : begin
				dis_control <= 4'b1110;
				led_dis <= disp_data_0;
			end
            1 : begin
				dis_control <= 4'b1101;
				led_dis <= disp_data_0;	
			end
            2 : begin
				dis_control <= 4'b1011;
				led_dis <= disp_data_0;	
			end
            3 : begin
				dis_control <= 4'b0111;
				led_dis <= disp_data_0;	
			end
			
			endcase
      end
	end
		
  /***********************************************************
   * Module Instantiation                                    *
   ***********************************************************/
   slowclock
      my_clock (
         .clk       (clk_50mhz),        	// I      50MHz
         .clk_800Hz (clk_800Hz)); 			// I      800Hz

endmodule
